AC82G41SLGQ3 Datasheet, PDF (443/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
Default
Value
RST/PWR
Description
4
RO
Invalidation Queue Error (IQE): Hardware detected an
error associated with the invalidation queue. This could be
due to either a hardware error while fetching a descriptor
from the invalidation queue, or hardware detecting an
erroneous or invalid descriptor in the invalidation queue. At
this time, a fault event may be generated based on the
0b
Core
programming of the Fault Event Control register.
Hardware implementations not supporting queued
invalidations implement this bit as Reserved.
3
RO
NOTE: This field is reserved as this feature is not
supported.
Advanced Pending Fault (APF): When this field is Clear,
hardware sets this field when the first fault record (at index
0) is written to a fault log. At this time, a fault event is
generated based on the programming of the Fault Event
Control register.
0b
Core
Software writing 1 to this field clears it. Hardware
implementations not supporting advanced fault logging
implement this bit as Reserved.
2
RO
NOTE: This field is reserved as this feature is not
supported.
Advanced Fault Overflow (AFO): Hardware sets this
field to indicate advanced fault log overflow condition. At
this time, a fault event is generated based on the
programming of the Fault Event Control register.
0b
Core
Software writing 1 to this field clears it. Hardware
implementations not supporting advanced fault logging
implement this bit as Reserved.
1
RO/P
0h
0
R/WC/P
0h
Core
Core
NOTE: This field is reserved as this feature is not
supported.
Primary Pending Fault (PPF): This field indicates if
there are one or more pending faults logged in the fault
recording registers. Hardware computes this field as the
logical OR of Fault (F) fields across all the fault recording
registers of this DMA-remapping hardware unit.
0 = No pending faults in any of the fault recording
registers.
1 = One or more fault recording registers has pending
faults. The FRI field is updated by hardware whenever
the PPF field is set by hardware. Also, depending on
the programming of Fault Event Control register, a
fault event is generated when hardware sets this field.
Primary Fault Overflow (PFO): Hardware sets this field
to indicate overflow of fault recording registers. Software
writing 1 clears this field.
Datasheet
443