AC82G41SLGQ3 Datasheet, PDF (391/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.9.10 KTIBA—KT IO Block Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
10-13h
00000001h
RO, R/W
32 bits
Reset: Host system Reset or D3->D0 transition.
Base Address for the 8byte IO space for KT.
Bit
31:16
15:3
2:1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
0000h
00b
1b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Base Address (BAR): This field provides the base
address of the I/O space (8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): This bit indicates a
request for I/O space
10.9.11 KTMBA—KT Memory Block Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
14-17h
00000000h
RO, R/W
32 bits
Reset: Host system Reset or D3->D0 transition
Base Address of Memory Mapped space.
Bit
Access
31:12
11:4
3
2:1
0
R/W
RO
RO
RO
RO
Default
Value
00000h
00h
0b
00b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Base Address (BAR): This field provides the base
address for Memory Mapped I,O BAR. Bits 31:12
correspond to address signals 31:12.
Reserved
Prefetchable (PF): This bit indicates that this range is not
pre-fetchable.
Type (TP): This field indicates that this range can be
mapped anywhere in 32-bit address space.
Resource Type Indicator (RTE): This bit indicates a
request for register memory space.
Datasheet
391