AC82G41SLGQ3 Datasheet, PDF (337/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.18 PMCS— PCI Power Management Control And Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
54-55h
0008h
R/W, RO, R/WC
16 bits
Bit
15
14:9
8
7:4
3
2
1:0
Access
R/WC
RO
R/W
RO
RO
RO
R/W
Default
Value
0b
000000b
0b
0000b
1b
0b
00b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
PME Status (PMES): The PME Status bit in HECI space
can be set to 1 by ARC FW performing a write into AUX
register to set PMES.
This bit is cleared by host processor writing a 1 to it.
ARC cannot clear this bit.
Host processor writes with value 0 have no effect on this
bit.
This bit is reset to 0 by MRST#.
Reserved.
PME Enable (PMEE): This bit is read/write, under control
of host software. It does not directly have an effect on PME
events. However, this bit is shadowed into AUX space so
ARC FW can monitor it. The ARC FW is responsible for
ensuring that FW does not cause the PME-S bit to
transition to 1 while the PMEE bit is 0, indicating that host
SW had disabled PME.
This bit is reset to 0 by MRST#.
Reserved
No_Soft_Reset (NSR): This bit indicates that when the
HECI host controller is transitioning from D3hot to D0 due
to power state command, it does not perform and internal
reset. Configuration context is Reserved.
Reserved
Power State (PS): This field is used both to determine
the current power state of the HECI host controller and to
set a new power state. The values are:
00 = D0 state
11 = D3HOT state
The D1 and D2 states are not supported for this HECI host
controller. When in the D3HOT state, the HBA’s
configuration space is available, but the register memory
spaces are not. Additionally, interrupts are blocked. This
field is visible to firmware through the H_PCI_CSR register,
and changes to this field may be configured by the
H_PCI_CSR register to generate an ME MSI.
Datasheet
337