AC82G41SLGQ3 Datasheet, PDF (63/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
3.3
PCI Memory Address Range (TOLUD – 4 GB)
This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
Device 0 exceptions are:
• Addresses decoded to the egress port registers (PXPEPBAR).
• Addresses decoded to the memory mapped range for internal (G)MCH registers
(GMCHBAR).
• Addresses decoded to the flat memory-mapped address spaced to access device
configuration registers (PCIEXBAR).
• Addresses decoded to the registers associated with the Direct Media Interface
(DMI) register memory range (DMIBAR).
With PCI Express port, there are two exceptions to this rule.
• Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
MLIMIT1, registers are mapped to PCI Express.
• Addresses decoded to the PCI Express prefetchable Memory Window defined by the
PMBASE1, PMLIMIT1, registers are mapped to PCI Express.
In integrated graphics configurations, there are exceptions to this rule (82Q45, 82Q43,
82B43, 82G45, 82G43, 82G41 GMCH only):
1. Addresses decoded to the IGD registers and internal graphics instruction port
(Function 0 MMADR, Function 1 MMADR).
2. Addresses decode to the internal graphics translation window (GMADR)
3. Addresses decode to the Internal graphics translation table (GTTADR)
In an Intel ME configuration, there are exceptions to this rule:
1. Addresses decoded to the ME Keyboard and Text MMIO range (EPKTBAR)
2. Addresses decoded to the ME HECI MMIO range (EPHECIBAR)
3. Addresses decoded to the ME HECI2 MMIO range (EPHECI2BAR)
In a Virtualization Technology (VT) enable configuration, there are exceptions to this
rule (82Q45 GMCH only):
1. Addresses decoded to the memory mapped window to Graphics VT remap engine
registers (GFXVTBAR)
2. Addresses decoded to the memory mapped window to DMI VC1 VT remap engine
registers (DMIVC1BAR)
3. Addresses decoded to the memory mapped window to ME VT remap engine
registers (VTMEBAR)
Addresses decoded to the memory mapped window to PEG/DMI VC0 VT remap engine
registers (VTDPVC0BAR)
Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The
exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with these ranges.
Datasheet
63