AC82G41SLGQ3 Datasheet, PDF (114/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
Access
Default
Value
RST/PWR
Description
2:1
R/W/L
00b
0
R/W/L
0b
Core
Core
TSEG Size (TSEG_SZ): Selects the size of the TSEG
memory block if enabled. Memory from the top of DRAM
space is partitioned away so that it may only be accessed
by the processor interface and only then when the SMM bit
is set in the request packet. Non-SMM accesses to this
memory region are sent to DMI when the TSEG memory
block is enabled.
00 = 1 MB TSEG. (TOLUD – GTT Graphics Memory Size –
Graphics Stolen Memory Size – 1M) to (TOLUD – GTT
Graphics Memory Size – Graphics Stolen Memory
Size).
01 = 2 MB TSEG (TOLUD – GTT Graphics Memory Size –
Graphics Stolen Memory Size – 2M) to (TOLUD – GTT
Graphics Memory Size – Graphics Stolen Memory
Size).
10 = 8 MB TSEG (TOLUD – GTT Graphics Memory Size –
Graphics Stolen Memory Size – 8M) to (TOLUD – GTT
Graphics Memory Size – Graphics Stolen Memory
Size).
11 = Reserved.
Once D_LCK has been set, these bits becomes read only.
TSEG Enable (T_EN): Enabling of SMRAM memory for
Extended SMRAM space only. When G_SMRAME = 1 and
TSEG_EN = 1, the TSEG is enabled to appear in the
appropriate physical address space. Note that once D_LCK
is set, this bit becomes read only.
5.1.30
Note:
TOM—Top of Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
A0-A1h
0001h
RO, R/W/L
16 bits
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
15:10
Access
RO
9:0
R/W/L
Default
Value
00h
001h
RST/PWR
Description
Core
Core
Reserved
Top of Memory (TOM): This register reflects the total
amount of populated physical memory. This is NOT
necessarily the highest main memory address (holes may
exist in main memory address map due to addresses
allocated for memory-mapped I/O). These bits correspond
to address bits 35:26 (64 MB granularity). Bits 25:0 are
assumed to be 0.
The (G)MCH determines the base of EP stolen memory by
subtracting the EP stolen memory size from TOM.
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Datasheet