AC82G41SLGQ3 Datasheet, PDF (236/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.7
CL1—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
Ch
00h
RW
8 bits
Bit
7:0
8.8
Access
RW
Default
Value
00h
RST/
PWR
Core
Description
Cache Line Size (Scratch pad): Implemented by PCI Express
devices as a read-write field for legacy compatibility purposes but has
no impact on any PCI Express device functionality.
HDR1—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
Eh
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Bit
7:0
8.9
Access
Default
Value
RO
01h
Description
Core
Header Type Register (HDR): Returns 01h to indicate that this is a
single function device with bridge header layout.
PBUSN1—Primary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
18h
00h
RO
8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
Bit
Access
Default
Value
RST/
PWR
Description
Primary Bus Number (BUSN): Configuration software typically
7:0
RO
00h
Core
programs this field with the number of the bus on the primary side of
the bridge. Since device #6 is an internal device and its primary bus
is always 0, these bits are read only and are hardwired to 0.
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Datasheet