AC82G41SLGQ3 Datasheet, PDF (122/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.39
SKPD—Scratchpad Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
DC-DFh
00000000h
R/W
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
Bit
31:0
Access
R/W
Default
Value
RST/PWR
Description
00000000h
Core
Scratchpad Data (SKPD): 1 DWord of data storage.
5.1.40 CAPID0—Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/PCI
E0-ECh
000000000000000000010C0009h
RO
104 bits
0h
Bit
103:28
27:24
23:16
15:8
Access
RO
RO
RO
RO
7:0
RO
Default
Value
0000b
1h
0Ch
00h
09h
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
CAPID Version (CAPIDV): This field has the value 0001b
to identify the first revision of the CAPID register definition.
CAPID Length (CAPIDL): This field has the value 0Ch to
indicate the structure length (12 bytes).
Next Capability Pointer (NCP): This field is hardwired to
00h indicating the end of the capabilities linked list.
Capability Identifier (CAP_ID): This field has the value
1001b to identify the CAP_ID assigned by the PCI SIG for
vendor dependent capability pointers.
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