AC82G41SLGQ3 Datasheet, PDF (425/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12 Intel^® Virtualization
Technology for Directed I/O
Registers (D0:F0) (Intel^®
82Q45 GMCH Only)
12.1 DMI and PEG VC0/VCp Remap Registers
Table 26. Intel^® Virtualization Technology For Directed I/O Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
0–3h
8–Fh
VER_REG
CAP_REG
Version Register
Capability Register
10–17h
18–1Bh
1C–1Fh
20–27h
ECAP_REG Extended Capability Register
GCMD_REG
GSTS_REG
Global Command Register
Global Status Register
RTADDR_REG Root-Entry Table Address Register
28–2Fh
CCMD_REG Context Command Register
34–37h
FSTS_REG Fault Status Register
38–3Bh
3C–3Fh
40–43h
44–47h
FECTL_REG Fault Event Control Register
FEDATA_REG Fault Event Data Register
FEADDR_REG Fault Event Address Register
FEUADDR_REG Fault Event Upper Address Register
58–5Fh
AFLOG_REG Advanced Fault Log Register
64–67h
68–6Bh
6C–6Fh
PMEN_REG Protected Memory Enable Register
PLMBASE_REG Protected Low-Memory Base Register
PLMLIMIT_REG Protected Low-Memory Limit Register
70–77h PHMBASE_REG Protected High-Memory Base Register
78–7Fh
PHMLIMIT_RE
G
Protected High-Memory Limit Register
100–107h
IVA_REG
Invalidate Address Register
00000010h
00C9008020
630272h
00000000000
01000h
00000000h
00000000h
00000000000
00000h
00000000000
00000h
00000000h
80000000h
00000000h
00000000h
00000000h
00000000000
00000h
00000000h
00000000h
00000000h
00000000000
00000h
00000000000
00000h
00000000000
00000h
RO
RO
RO
RO, W
RO
R/W, RO
W, R/W, RO
RO, RO/P,
R/WC/P
R/W, RO
RO, R/W
RO, R/W
RO
RO
RO, R/W
R/W, RO
R/W, RO
RO, R/W
R/W, RO
W, RO
Datasheet
425