AC82G41SLGQ3 Datasheet, PDF (400/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.2 KTTHR—KT Transmit Holding Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
0h
00h
WO
8 bits
Reset: Host System Reset or D3->D0 transition.
This implements the KT Transmit Data register. Host access to this address, depends on
the state of the DLAB bit {KTLCR[7]). It must be "0" to access the KTTHR.
THR:
When host wants to transmit data in the non-FIFO mode, it writes to this register. In
FIFO mode, writes by host to this address cause the data byte to be written by
hardware to ME memory (THR FIFO).
Bit
Access
Default
Value
RST/PWR
Description
7:0
WO
Transmit Holding Register (THR): Implements the
00h
Core
Transmit Data register of the Serial Interface. If the Host
does a write, it writes to the Transmit Holding Register.
10.10.3 KTDLLR—KT Divisor Latch LSB Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
0h
00h
R/W/V
8 bits
Reset: Host System Reset or D3->D0 transition.
This register implements the KT DLL register. Host can Read/Write to this register only
when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the
KTRBR depending on Read or Write.
This is the standard Serial Port Divisor Latch register. This register is only for software
compatibility and does not affect performance of the hardware.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
Divisor Latch LSB (DLL): Implements the DLL register of
the Serial Interface.
400
Datasheet