AC82G41SLGQ3 Datasheet, PDF (54/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
graphics device in VGA (non-linear) and Native (linear) modes. (0–256 MB
options).
— GGCGGMS – GMCH graphics control register, GTT Graphics Memory Size
(82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41 GMCH only). This register is
used to select the amount of main memory that is pre-allocated to support the
Internal Graphics Translation Table. (0–2 MB options).
• Device 1
— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access
window
— IOBASE1/IOLIMIT1 – PCI Express port I/O access window.
• Device 2, Function 0 (82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41 GMCH only)
— MMADR – IGD registers and internal graphics instruction port. (512 KB window)
— IOBAR – I/O access window for internal graphics. Though this window address/
data register pair, using I/O semantics, the IGD and internal graphics
instruction port registers can be accessed. Note that this allows accessing the
same registers as MMADR. In addition, the IOBAR can be used to issue writes
to the GTTADR table.
— GMADR – Internal graphics translation window. (128 MB, 256 MB or 512 MB
window).
— GTTADR – Internal graphics translation table location. (1 MB window). Note
that the Base of GTT stolen Memory register (Device 0 A8) indicates the
physical address base which is 1 MB aligned.
• Device 2, Function 1 (82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41 GMCH only)
— MMADR – Function 1 IGD registers and internal graphics instruction port.
(512 KB window)
• Device 3
— ME Control
• Device 6, Function 0 (82P45 MCH only)
— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access
window
— IOBASE1/IOLIMIT1 – PCI Express port IO access window.
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designers' responsibility to limit memory population so that adequate PCI,
PCI Express, High BIOS, and PCI Express Memory Mapped space, and APIC
memory space can be allocated.
2. In the case of overlapping ranges with memory, the memory decode will be given
priority. This is an Intel Trusted Execution Technology requirement. It is necessary
to get Intel TET protection checks, avoiding potential attacks.
3. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
4. Accesses to overlapped ranges may produce indeterminate results.
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Datasheet