AC82G41SLGQ3 Datasheet, PDF (136/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
21
20
19:17
16
15:14
13:10
9:1
0
Access
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
Default
Value
0b
0b
000b
0b
00b
0010b
000000000
b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Rank 1 Population (sd0_cr_rankpop1):
1 = Rank 1 populated
0 = Rank 1 not populated
This register is locked by ME stolen Memory lock.
Rank 0 Population (sd0_cr_rankpop0):
1 = Rank 0 populated
0 = Rank 0 not populated
This register is locked by ME stolen Memory lock.
CKE pulse width requirement in low phase
(sd0_cr_cke_pw_lh_safe): This configuration register
indicates CKE pulse width requirement in low phase. This
field corresponds to tCKE (low) in the DDR Specification.
Enable CKE toggle for PDN entry/exit
(sd0_cr_pdn_enable): This configuration bit indicates
that the toggling of CKEs (for PDN entry/exit) is enabled.
Reserved
Minimum Powerdown exit to Non-Read command
spacing (sd0_cr_txp): This configuration register
indicates the minimum number of clocks to wait following
assertion of CKE before issuing a non-read command.
1010–1111=Reserved.
0010–1001=2–9clocks.
0000–0001=Reserved.
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt):
This configuration register indicates the Self refresh exit
count. (Program to 255). This field corresponds to tXSNR/
tXSRD in the DDR Specification.
Indicates Only 1 DIMM Populated
(sd0_cr_singledimmpop): This configuration register
indicates the that only 1 DIMM is populated.
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Datasheet