AC82G41SLGQ3 Datasheet, PDF (380/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.8.4
IDEPBMDS1R—IDE Primary Bus Master Device Specific 1
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
3h
00h
R/W
8 bits
Reset: ME system Reset
This register implements the bus master Device Specific 1 register of the primary
channel. This register is programmed by the Host for device specific data if any.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Device Specific Data1 (DSD1): Device Specific Data.
10.8.5
IDEPBMDTPR0—IDE Primary Bus Master Descriptor Table
Pointer Register Byte 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
4h
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the primary channel. This register is
read/write by the HOST interface.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 0 (DTPB0):
10.8.6
IDEPBMDTPR1—IDE Primary Bus Master Descriptor Table
Pointer Register Byte 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
5h
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Byte 1 (of four bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the primary channel. This register is
programmed by the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 1 (DTPB1):
380
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