AC82G41SLGQ3 Datasheet, PDF (397/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.9.25 MID—Message Signaled Interrupt Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
D0-D1h
0005h
RO
16 bits
Message Signalled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a DWORD memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
Bit
15:8
7:0
Access
RO
RO
Default
Value
00h
05h
RST/PWR
Description
Core
Core
Next Pointer (NEXT): This value indicates this is the last
item in the list.
Capability ID (CID): This field value of Capabilities ID
indicates device is capable of generating MSI.
10.9.26 MC—Message Signaled Interrupt Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
D2-D3h
0080h
RO, R/W
16 bits
Reset: Host System Reset or D3->D0 transition.
This register provides System Software control over MSI.
Bit
15:8
7
6:4
3:1
0
Access
RO
RO
R/W
RO
R/W
Default
Value
00h
1b
000b
000b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
64 Bit Address Capable (C64): Capable of generating
64-bit and 32-bit messages.
Multiple Message Enable (MME): These bits are R/W for
software compatibility, but only one message is ever sent
by the PT function.
Multiple Message Capable (MMC): Only one message is
required.
MSI Enable (MSIE): If set, MSI is enabled and traditional
interrupt pins are not used to generate interrupts.
Datasheet
397