AC82G41SLGQ3 Datasheet, PDF (412/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.2
TXT.ESTS—TXT Error Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
8h
00h
RWC, RO
8 bits
This register is used to read the status associated with various errors that might be
detected. All defined bits in this register are sticky.
Bit Access
7
RWC
6
RWC
5:1 RWC
0
RO
Default
Value
Description
0b
Reserved
TXT Wake Error Status (TXT.WAKE-ERROR.STS): The chipset sets this bit
when it detects that there might have been secrets in memory and a reset or
power failure occurred.
If this bit is set after a system reset, the chipset will prevent memory accesses
until specifically enabled. The software that is authorized to enable the memory
accesses will also be responsible for clearing the secrets from memory.
0b
Software can read chipset-specific registers to determine the specific cause of the
error. The location of those bits is beyond the scope of this specification.
On a reset, if CPU_RESET_DONE_ACK_SECRET is received, then this bit is set to
'1'.
On a reset, if CPU_RESET_DONE_ACK is received, then this bit is cleared to '0'.
Software can clear this bit by writing a '1' to it.
This bit must be cleared if a read to 0xFED4_0000 returns a 1 in bit 0.
0b
Reserved
TXT Reset Status (TXT.TXT_RESET.STS): The chipset sets this bit to ‘1’ to
indicate that the platform experienced a TXT reset. To maintain TXT integrity,
while this bit is set, a TXT measured environment cannot be established;
consequently Safer Mode Extension (SMX) instructions GETSEC [ENTERACCS] and
0b
GETSEC [SENTER] will fail. See Chapter 6, “Safer Mode Extensions Reference” of
Intel^® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
Reads to the TXT public space and other non-SMX instructions will continue to
work. This bit must be cleared to re-enable TXT on the platform. Note: This bit is
sticky and will only be cleared on a power cycle.
412
Datasheet