AC82G41SLGQ3 Datasheet, PDF (138/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
21:20
19:18
17:16
15:14
13:0
Access
R/W
R/W
R/W
R/W
R/W
Default
Value
00b
00b
00b
00b
001100001
10000b
RST/PWR
Description
Core
Core
Core
Core
Core
DRAM Refresh Hysterisis (REFHYSTERISIS):
Hysterisis level - Useful for dref_high watermark cases.
The dref_high flag is set when the dref_high watermark
level is exceeded, and is cleared when the refresh count is
less than the hysterisis level. This bit should be set to a
value less than the high watermark level.
00 = 3
01 = 4
10 = 5
11 = 6
DRAM Refresh Panic Watermark (REFPANICWM):
When the refresh count exceeds this level, a refresh
request is launched to the scheduler and the dref_panic
flag is set.
00 = 5
01 = 6
10 = 7
11 = 8
DRAM Refresh High Watermark (REFHIGHWM): When
the refresh count exceeds this level, a refresh request is
launched to the scheduler and the dref_high flag is set.
00 = 3
01 = 4
10 = 5
11 = 6
DRAM Refresh Low Watermark (REFLOWWM): When
the refresh count exceeds this level, a refresh request is
launched to the scheduler and the dref_low flag is set.
00 = 1
01 = 2
10 = 3
11 = 4
Refresh Counter Time Out Value (REFTIMEOUT):
Program this field with a value that will provide 7.8 us at
the memory clock frequency. At various memory clock
frequencies, this results in the following values:
266 MHz -> 820 hex
333 MHz -> A28 hex
400 MHz -> C30 hex
533 MHz -> 104B hex
666 MHz -> 1450 hex
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Datasheet