AC82G41SLGQ3 Datasheet, PDF (427/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
47:40
39
38
37:34
33:24
23
22
Access
RO
RO
RO
RO
RO
RO
RO
Default
Value
00000000b
1b
0b
0000b
020h
0b
1b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Number of Faultrecording Registers (NFR): This field
indicates a value of N-1, where N is the number of fault
recording registers supported by hardware.
Implementations must support at least one fault recording
register (NFR = 0) for each DMAremapping hardware unit
in the platform.
The maximum number of fault recording registers per
DMA-remapping hardware unit is 256.
Bit 40 in the capability register is the least significant bit of
the NFR field (47:40).
Page Selective Invalidation Support (PSI):
0 = DMAr engine does not support page selective
invalidations
1 = DMAr engine does support page-selective IOTLB
invalidations. The MAMV field indicates the maximum
number of contiguous translations that may be
invalidated in a single request.
Reserved
Super Page Support (SPS): This field indicates the super
page sizes supported by hardware. A value of 1 in any of
these bits indicates the corresponding super-page size is
supported. The super-page sizes corresponding to various
bit positions within this field are:
0 = 21-bit offset to page frame
1 = 30-bit offset to page frame
2 = 39-bit offset to page frame
3 = 48-bit offset to page frame
Fault-recording Register offset (FRO): This field
specifies the location to the first fault recording register
relative to the register base address of this DMA-
remapping hardware unit. If the register base address is X,
and the value reported in this field is Y, the address for the
first fault recording register is calculated as X+(16*Y).
Isochrony (Isoch):
0 = DMA-remapping hardware unit has no critical
isochronous requesters in its scope.
1 = DMA-remapping hardware unit has one or more critical
isochronous requesters in its scope.
To ensure isochronous performance, software must ensure
invalidation operations do not impact active DMA streams.
This implies that when DMA is active, software perform
page-selective invalidations (instead of coarser
invalidations).
Zero Length Read (ZLR):
0 = Remapping hardware unit blocks (and treats as fault)
zero length DMA read requests to write-only pages.
1 = Remapping hardware unit supports zero length DMA
read requests to write-only pages.
Datasheet
427