AC82G41SLGQ3 Datasheet, PDF (151/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.32
EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A08-A09h
0000h
R/W
16 bits
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch0 Rank0, 1:
Ch0 Rank2, 3:
Ch1 Rank0, 1:
Ch1 Rank2, 3:
108h–109h
10Ah–10Bh
188h–189h
18Ah–18Bh
Bit
15:8
7:0
Access
R/W
R/W
Default
Value
00h
00h
RST/PWR
Description
Core
Core
Channel 0 DRAM Rank-1 Attributes (C0DRA1): This
field defines DRAM pagesize/number-of-banks for rank1
for given channel.
Channel 0 DRAM Rank-0 Attributes (C0DRA0): This
field defines DRAM pagesize/number-of-banks for rank0
for given channel.
5.2.33
EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A0A-A0Bh
0000h
R/W
16 bits
See C0DRA01 for detailed descriptions.
Bit
15:8
7:0
Access
R/W
R/W
Default
Value
00h
00h
RST/PWR
Description
Core
Core
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This
field defines DRAM pagesize/number-of-banks for rank3
for given channel.
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This
field defines DRAM pagesize/number-of-banks for rank2
for given channel.
Datasheet
151