AC82G41SLGQ3 Datasheet, PDF (125/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.1
CHDECMISC—Channel Decode Miscellaneous
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
111h
00h
R/W/L, R/W
8 bits
This register provides miscellaneous CHDEC/MAGEN configuration bits.
Bit
Access
Default
Value
RST/PWR
Description
7
R/W/L
0b
Core
Enhanced Address for DIMM Select (ENHDIMMSEL):
This bit can be set when enhanced mode of addressing for
ranks are enabled and all four ranks are populated with
equal amount of memory. This should be disabled when EP
is present.
0 = Use Standard methods for DIMM Select.
1 = Use Enhanced Address as DIMM Select.
This field is locked by ME stolen Memory lock.
6:5
R/W/L
00b
4
R/W/L
0b
3
R/W/L
0b
Core
Core
Core
Enhanced Mode Select (ENHMODESEL):
00 = Swap Enabled for Bank Selects and Rank Selects
01 = XOR Enabled for Bank Selects and Rank Selects
10 = Swap Enabled for Bank Selects only
11 = XOR Enabled for Bank Select only
This field is locked by ME stolen Memory lock.
L-Shaped GFX Tile Cycle (LGFXTLCYC): This bit forces
graphics tiled cycles in L-shaped memory configuration to
modify bit 6 of the address. This field should be set to 1
only when L-mode memory configuration is enabled and
should be set to 0 for all other memory configurations.
This bit is locked by ME stolen Memory lock.
Ch1 Enhanced Mode (CH1_ENHMODE): This bit
indicates that enhanced addressing mode of operation is
enabled for ch1.
Enhanced addressing mode of operation should be enabled
only when both the channels are equally populated with
same size and same type of DRAM memory.
An added restriction is that the number of ranks/channel
has to be 1, 2, or 4.
NOTE: If any of the channels is in enhanced mode, the
other channel should also be in enhanced mode.
This bit is locked by ME stolen Memory lock.
Datasheet
125