AC82G41SLGQ3 Datasheet, PDF (311/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.2.23
GDRST—Mirror of Device 2 Function 0 Graphics Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
C0h
00h
RO
8 bits
This register is a mirror of Graphics Reset Register in Device 2.
Bit
Access
Default
Value
RST/
PWR
Description
7:4
RO
3:2
RO
1
RO
0
RO
0h
Core Reserved
Graphics Reset Domain (GRDOM):
00 = Full Graphics Reset will be performed (both render and
display clock domain resets asserted)
00b
FLR, Core
01 = Render Only Reset (render clock domain reset asserted)
10 = Reserved (Invalid Programming)
11 = Media Only Reset (Media domain reset get asserted)
0b
Core
Reserved
Graphics Reset Enable (GR): Setting this bit asserts
graphics-only reset. The clock domains to be reset are
determined by GRDOM. Hardware resets this bit when the reset
is complete. Setting this bit without waiting for it to clear, is
undefined behavior.
Once this bit is set to a 1, all graphics core MMIO registers are
returned to power on default state. All Ring buffer pointers are
reset, command stream fetches are dropped and ongoing
0b
Core ^{render pipeline processing is halted, state machines and State}
Variables returned to power on default state. If the Display is
reset, all display engines are halted (garbage on screen). VGA
memory is not available, Store DWORDs and interrupts are not
ensured to be completed. Device 2 I/O registers are not
available.
Device 2 Configuration registers continue to be available while
Graphics reset is asserted.
This bit is hardware auto-clear.
Datasheet
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