AC82G41SLGQ3 Datasheet, PDF (243/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.18
PMLIMIT1—Prefetchable Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
26–27h
0001h
RO, RW
16 bits
This register in conjunction with the corresponding Upper Limit Address register
controls the processor to PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode,
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1 MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e., prefetchable) from the processor perspective.
Bit
15:4
3:0
Access
RW
RO
Default
Value
000h
1h
RST/
PWR
Core
Core
Description
Prefetchable Memory Address Limit (PMLIMIT): This field
corresponds to A[31:20] of the upper limit of the address range
passed to PCI Express.
64-bit Address Support: This field indicates that the upper 32 bits
of the prefetchable memory region limit address are contained in the
Prefetchable Memory Base Limit Address register at 2Ch
Datasheet
243