AC82G41SLGQ3 Datasheet, PDF (267/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.47
VCECH—Virtual Channel Enhanced Capability
Header
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
100–103h
14010002h
RO
32 bits
This register indicates PCI Express device Virtual Channel capabilities. Extended
capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability
structures.
Bit
31:20
19:16
15:0
Access
RO
RO
RO
Default
Value
140h
1h
0002h
RST/
PWR
Core
Core
Core
Description
Pointer to Next Capability (PNC): The Link Declaration Capability
is the next in the PCI Express extended capabilities list.
PCI Express Virtual Channel Capability Version (PCIEVCCV):
Hardwired to 1 to indicate compliances with the 1.1 version of the PCI
Express specification.
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0002h identifies this
linked list item (capability structure) as being for PCI Express Virtual
Channel registers.
8.48
PVCCAP1—Port VC Capability Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
104–107h
00000000h
RO
32 bits
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
Bit
31:7
6:4
3
2:0
Access
RO
RO
RO
RO
Default
Value
00000h
000b
0b
000b
RST/
PWR
Core
Core
Core
Core
Description
Reserved
Low Priority Extended VC Count (LPEVCC): This field indicates
the number of (extended) Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group that has the lowest
priority with respect to other VC resources in a strict-priority VC
Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
Extended VC Count (EVCC): This field indicates the number of
(extended) Virtual Channels in addition to the default VC supported
by the device.
Datasheet
267