AC82G41SLGQ3 Datasheet, PDF (215/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
Default
Value
RST/PWR
Description
9:7
R/W/P
000b
6
R/W/P
0b
5
R/W
0b
4
R/W/P
0b
Core
Core
Core
Core
Transmit Margin (txmargin): This field controls the
value of the non-deemphasized voltage level at the
Transmitter pins. This field is reset to 000b on entry to the
LTSSM Polling.Configuration substates.
000 =
Normal operating range
001 =
800–1200 mV for full swing and 400–700
mV for half-swing
010 – (n-1) =
Values must be monotonic with a non-
zero slope. The value of n must be
greater than 3 and less than 7. At least
two of these must be below the normal
operating range
n=
200–400 mV for full-swing and 100–200
mV for half-swing
n – 111 =
reserved
Components that support only the 2.5 GT/s speed are
permitted to hardwire this bit to 0b.
When operating in 5 GT/s mode with full swing, the
deemphasis ratio must be maintained within ±1 dB from
the specification defined operational value (either -3.5 or
-6 dB).
Selectable De-emphasis (selectabledeemphasis):
When the Link is operating at 5 GT/s speed, selects the
level of de-emphasis.
1 = 3.5 dB
0 = 6 dB
Default value is implementation specific, unless a specific
value is required for a selected form factor or platform.
When the Link is operating at 2.5 GT/s speed, the setting
of this bit has no effect. Components that support only the
2.5 GT/s speed are permitted to hardwire this bit to 0b.
Hardware Autonomous Speed Disable (HASD): When
set to 1, this bit disables hardware from changing the link
speed for reasons other than attempting to correct
unreliable link operation by reducing link speed.
Enter Compliance (EC): Software is permitted to force a
link to enter Compliance mode at the speed indicated in
the Target Link Speed field by setting this bit to 1 in both
components on a link and then initiating a hot reset on the
link.
Datasheet
215