AC82G41SLGQ3 Datasheet, PDF (216/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
Default
Value
RST/PWR
Description
Target Link Speed (TLS): For Downstream ports, this
field sets an upper limit on link operational speed by
restricting the values advertised by the upstream
component in its training sequences.
0001 = 2.5 Gb/s Target Link Speed
0010 = 5 Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond
to a speed included in the Supported Link Speeds field, the
3:0
R/W
2h
Core
result is undefined.
The default value of this field is the highest link speed
supported by the component (as reported in the
Supported Link Speeds field of the Link Capabilities
Register) unless the corresponding platform / form factor
requires a different default value.
For both Upstream and Downstream ports, this field is
used to set the target compliance mode speed when
software is using the Enter Compliance bit to force a link
into compliance mode.
6.1.51
LSTS2—Link Status 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
D2-D3h
0000h
RO
16 bits
Bit
15:1
0
Access
RO
RO
Default
Value
0000h
0b
RST/PWR
Description
Core
Core
Reserved
Current De-emphasis Level (CURDELVL): When the
Link is operating at 5 GT/s speed, this reflects the level of
de-emphasis.
1 = 3.5 dB
0 = 6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.
216
Datasheet