AC82G41SLGQ3 Datasheet, PDF (120/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.37
ERRCMD—Error Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
CA-CBh
0000h
R/W, RO
16 bits
This register controls the (G)MCH responses to various system errors. Since the
(G)MCH does not have an SERRB signal, SERR messages are passed from the (G)MCH
to the ICH over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device 0 via the PCI Command register.
Bit
15:12
Access
RO
Default
Value
0h
11
R/W
0b
10
RO
0b
9
R/W
0b
8
R/W
0b
7
R/W
0b
6:2
RO
00h
1
R/W
0b
0
R/W
0b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
Description
Reserved
SERR on (G)MCH Thermal Sensor Event (TSESERR):
1 = The (G)MCH generates a DMI SERR special cycle when bit 11 of
the ERRSTS is set. The SERR must not be enabled at the same
time as the SMI for the same thermal sensor event.
0 = Reporting of this condition via SERR messaging is disabled.
Reserved
SERR on LOCK to non-DRAM Memory (LCKERR):
1 = The (G)MCH will generate a DMI SERR special cycle whenever a
processor lock cycle is detected that does not hit DRAM.
0 = Reporting of this condition via SERR messaging is disabled.
SERR on DRAM Refresh Timeout (DRTOERR):
1 = The (G)MCH generates a DMI SERR special cycle when a DRAM
Refresh timeout occurs.
0 = Reporting of this condition via SERR messaging is disabled.
SERR on DRAM Throttle Condition (DTCERR):
1 = The (G)MCH generates a DMI SERR special cycle when a DRAM
Read or Write Throttle condition occurs.
0 = Reporting of this condition via SERR messaging is disabled.
Reserved
SERR Multiple-Bit DRAM ECC Error (DMERR):
1 = The (G)MCH generates a SERR message over DMI when it
detects a multiple-bit error reported by the DRAM controller.
0 = Reporting of this condition via SERR messaging is disabled. For
systems not supporting ECC, this bit must be disabled.
SERR on Single-bit ECC Error (DSERR):
1 = The (G)MCH generates a SERR special cycle over DMI when the
DRAM controller detects a single bit error.
0 = Reporting of this condition via SERR messaging is disabled.
For systems that do not support ECC, this bit must be disabled.
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Datasheet