AC82G41SLGQ3 Datasheet, PDF (184/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
12
11
10:9
8
7
6
5
4:0
Access
R/WC
RO
RO
R/WC
RO
RO
RO
RO
Default
Value
0b
0b
00b
0b
0b
0b
0b
00h
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Received Target Abort (RTA): This bit is set when the
Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device
itself) receives a Completion with Completer Abort
Completion Status.
Signaled Target Abort (STA): Not Applicable or
Implemented. Hardwired to 0. The (G)MCH does not
generate Target Aborts (the (G)MCH will never complete a
request using the Completer Abort Completion status.
DEVSELB Timing (DEVT): Not Applicable or
Implemented. Hardwired to 0.
Master Data Parity Error (SMDPE): When set, this bit
indicates that the MCH received across the link (upstream)
a Read Data Completion Poisoned TLP (EP=1). This bit can
only be set when the Parity Error Enable bit in the Bridge
Control register is set.
Fast Back-to-Back (FB2B): Not Applicable or
Implemented. Hardwired to 0.
Reserved
66/60 MHz capability (CAP66): Not Applicable or
Implemented. Hardwired to 0.
Reserved
6.1.15
MBASE1—Memory Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
20-21h
FFF0h
R/W, RO
16 bits
This register controls the processor to PCI Express non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode, address bits A[19:0] are assumed to be
0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
Bit
15:4
3:0
Access
R/W
RO
Default
Value
FFFh
0h
RST/PWR
Description
Core
Core
Memory Address Base (MBASE): This field corresponds
to A[31:20] of the lower limit of the memory range that
will be passed to PCI Express.
Reserved
184
Datasheet