AC82G41SLGQ3 Datasheet, PDF (272/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.55 ESD—Element Self Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
144–147h
03000100h
RO, RWO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
31:24
23:16
15:8
7:4
3:0
Access
RO
RWO
RO
RO
RO
Default
Value
03h
00h
01h
0h
0h
RST/
PWR
Core
Core
Core
Core
Core
Description
Port Number (PN): This field specifies the port number associated
with this element with respect to the component that contains this
element. This port number value is used by the egress port of the
component to provide arbitration to this Root Complex Element.
Component ID (CID): This field indicates the physical component
that contains this Root Complex Element.
Number of Link Entries (NLE): This field indicates the number of
link entries following the Element Self Description. This field reports 1
(to Egress port only as we don't report any peer-to-peer capabilities in
our topology).
Reserved
Element Type (ET): This field indicates Configuration Space
Element.
8.56 LE1D—Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
150–153h
00000000h
RO, RWO
32 bits
This register provides the first part of a Link Entry that declares an internal link to
another Root Complex Element.
Bit
31:24
23:16
15:2
1
0
Access
RO
RWO
RO
RO
RWO
Default
Value
00h
00h
0000h
0b
0b
RST/
PWR
Core
Core
Core
Core
Core
Description
Target Port Number (TPN): This field specifies the port number
associated with the element targeted by this link entry (Egress Port).
The target port number is with respect to the component that contains
this element as specified by the target component ID.
Target Component ID (TCID): This field identifies the physical or
logical component that is targeted by this link entry.
Reserved
Link Type (LTYP): This bit indicates that the link points to
memory–mapped space (for RCRB). The link address specifies the 64-
bit base address of the target RCRB.
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
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Datasheet