AC82G41SLGQ3 Datasheet, PDF (287/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.20
MAXLAT—Maximum Latency
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
3Fh
00h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
Maximum Latency Value (MLV): The IGD has no
00h
Core
specific requirements for how often it needs to access the
PCI bus.
9.1.21
CAPID0—Capability Identifier
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/2/0/PCI
40-4Ch
000000000000000000010C0009h
RO
104 bits
0h
This register control of bits in this register are only required for customer visible
component differentiation.
Bit
103:28
27:24
Access
RO
RO
23:16
RO
15:8
RO
7:0
RO
Default
Value
0000b
1h
0Ch
00h
09h
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
CAPID Version (CAPIDV): This field has the value
0001b to identify the first revision of the CAPID register
definition.
CAPID Length (CAPIDL): This field has the value 0Ch to
indicate the structure length (12 bytes).
Next Capability Pointer (NCP): This field is hardwired
to 00h indicating the end of the capabilities linked list.
Capability Identifier (CAP_ID): This field has the value
1001b to identify the CAP_ID assigned by the PCI SIG for
vendor dependent capability pointers.
Datasheet
287