AC82G41SLGQ3 Datasheet, PDF (16/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

13.5.2.1 High Definition Multimedia Interface (Intel^® 82G45, 82G43, 82G41,
82B43 GMCH Only).................................................................. 536
13.5.2.2 Digital Video Interface (DVI) ..................................................... 537
13.5.2.3 DDPC_CTRLDATA and DDPC_CTRLCLK ....................................... 537
13.5.2.4 Display Port............................................................................ 538
13.5.2.5 Auxiliary Channel (AUX CH) ...................................................... 538
13.5.2.6 PEG Mapping of digital display signals ........................................ 538
13.5.2.7 Multiplexed Digital Display Channels –
Intel^® SDVOB and Intel^® SDVOC .............................................. 540
13.5.3 Multiple Display Configurations ............................................................... 542
13.5.3.1 High Bandwidth Digital Content Protection (HDCP) ....................... 542
13.6 Intel^® Virtualization Technology for I/O Devices (Intel^® 82Q45 GMCH Only) ............ 543
13.6.1 Overview ............................................................................................. 543
13.6.2 Embedded IT Client Usage Model ............................................................ 543
13.6.2.1 Intel Virtualization Technology for I/O Devices Enables................. 544
13.6.2.2 Hardware Versus Software Virtualization .................................... 544
13.6.2.3 Hardware Virtualization Advantages ........................................... 544
13.7
13.8
13.6.3 Concept of DMA Address Remapping ....................................................... 544
Intel^® Trusted Execution Technology (Intel^® TXT)
(Intel^® 82Q45 and 82Q43 GMCH Only)............................................................... 545
Intel^® Management Engine (ME) Subsystem ....................................................... 546
13.8.1 ME Host Visible Functional Blocks............................................................ 546
13.8.2 ME Power States................................................................................... 547
13.8.3 Host/ME State Transitions ...................................................................... 547
13.9 Thermal Sensor ............................................................................................... 548
13.9.1 PCI Device 0, Function 0........................................................................ 548
13.9.2 GMCHBAR Thermal Sensor Registers ....................................................... 548
13.10 Power Management.......................................................................................... 549
13.10.1Main memory Power Management........................................................... 549
13.10.2Interface Power States Supported ........................................................... 550
13.10.3Chipset State Combinations ................................................................... 551
13.11 Clocking ......................................................................................................... 553
14 Electrical Characteristics........................................................................................ 555
14.1 Absolute Minimum and Maximum Ratings............................................................ 555
14.2 Current Consumption ....................................................................................... 556
14.3 (G)MCH Buffer Supply and DC Characteristics...................................................... 560
14.3.1 I/O Buffer Supply Voltages..................................................................... 560
14.3.2 General DC Characteristics..................................................................... 562
14.3.3 R, G, B / CRT DAC Display DC Characteristics (Intel^® 82Q45, 82Q43, 82B43,
82G45, 82G43, 82G41 GMCH Only)......................................................... 566
14.3.4 Di/dt Characteristics.............................................................................. 566
15 Ballout and Package Specifications ........................................................................ 569
15.1 Ballout ........................................................................................................... 569
15.2 Package Specifications...................................................................................... 597
16 Testability.............................................................................................................. 599
16.1 JTAG Boundary Scan ........................................................................................ 599
16.1.1 TAP Instructions and Opcodes ................................................................ 600
16.1.2 TAP interface and timings. ..................................................................... 600
16.2 XOR Test Mode Initialization.............................................................................. 602
16.2.1 XOR Chain Definition ............................................................................. 603
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Datasheet