AC82G41SLGQ3 Datasheet, PDF (232/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.2
DID1—Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
2–3h
29E9h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Bit
15:8
7:4
3:0
Access
RO
RO
RO
Default
Value
29h
Eh
9h
RST/
PWR
Core
Core
Core
Description
Device Identification Number (DID1(UB)): Identifier assigned to
the MCH device #6 (virtual PCI-to-PCI bridge, PCI Express port).
Device Identification Number (DID1(HW)): Identifier assigned
to the MCH device #6 (virtual PCI-to-PCI bridge, PCI Express port).
Device Identification Number (DID1(LB)): Identifier assigned to
the MCH device #6 (virtual PCI-to-PCI bridge, PCI Express port).
8.3
PCICMD1—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
4–5h
0000h
RO, RW
16 bits
Bit
15:11
10
9
Access
RO
RW
RO
Default
Value
00h
0b
0b
RST/
PWR
Core
Core
Core
Description
Reserved
INTA Assertion Disable (INTAAD):
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages. Any
INTA emulation interrupts already asserted must be de-asserted
when this bit is set.
This bit only affects interrupts generated by the device (PCI INTA
from a PME event) controlled by this command register. It does not
affect upstream MSIs, upstream PCI INTA-INTD assert and de-assert
messages.
Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented.
Hardwired to 0.
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Datasheet