AC82G41SLGQ3 Datasheet, PDF (43/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Signal Description
2.6
Clocks, Reset, and Miscellaneous
Signal Name
HPL_CLKINP
HPL_CLKINN
EXP_CLKP
EXP_CLKN
DPL_REFCLKINN
DPL_REFCLKINP
DPL_REFSSCLKINP
DPL_REFSSCLKINN
RSTINB
CL_PWROK
EXP_SLR
BSEL[2:0]
EXP_SM
Type
I
CMOS
I
CMOS
I
CMOS
I
CMOS
I
SSTL
I/O
SSTL
I
CMOS
I
CMOS
I
GTL+
Description
Differential Host Clock In: These pins receive a differential
host clock from the external clock synthesizer. This clock is
used by all of the (G)MCH logic that is in the Host clock
domain.
Differential Primary PCI Express Clock In: These pins
receive a differential 100 MHz Serial Reference clock from the
external clock synthesizer. This clock is used to generate the
clocks necessary for the support of Primary PCI Express and
DMI.
Display PLL Differential Clock In: Tie DPL_REFCLKINP to
V_CC and tie DPL_REFCLKINN to ground when not using DP.
Display PLL Differential Clock In: Tie DPL_REFSSCLKINP
to V_CC and tie DPL_REFSSCLKINN to ground when not using
DP.
Reset In: When asserted, this signal will asynchronously
reset the (G)MCH logic. This signal is connected to the
PCIRST# output of the ICH. All PCI Express output signals
and DMI output signals will also tri-state compliant to PCI
Express Specification, Revision 2.0.
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3 V tolerant.
CL Power OK: When asserted, CL_PWROK is an indication to
the (G)MCH that core power (VCC_CL) has been stable for at
least 10 us.
PCI Express* Static Lane Reversal/Form Factor
Selection: (G)MCH’s PCI Express lane numbers are reversed
to differentiate Balanced Technology Extended (BTX) and ATX
form factors.
0 = (G)MCH PCI Express lane numbers are reversed (BTX)
1 = Normal operation (ATX)
Bus Speed Select: At the de-assertion of PWROK, the value
sampled on these pins determines the expected frequency of
the bus.
Concurrent PCI Express Port Enable: Concurrent SDVO
and PCI Express
0 = Only SDVO or PCI Express is operational.
1 = Both SDVO and PCI Express are operating simultaneously
via the PCI Express port.
PWROK
DPRSTPB
I/O
SSTL
O
HVCMOS
NOTE: For the 82P45 and 82P42 MCH, this signal should be
pulled low.
Power OK: When asserted, PWROK is an indication to the
(G)MCH that core power has been stable for at least 10 us.
Advanced Power Management Signal
Datasheet
43