AC82G41SLGQ3 Datasheet, PDF (17/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Figures
1 Intel® Q45, Q43, B43, G45, G43 Chipset System Block Diagram Example ....................... 24
2 Intel® P45, P43 Chipset System Block Diagram Example .............................................. 25
3 Intel® G41 Express Chipset System Block Diagram Example ......................................... 26
4 System Address Ranges............................................................................................ 56
5 DOS Legacy Address Range....................................................................................... 57
6 Main Memory Address Range ..................................................................................... 61
7 PCI Memory Address Range ...................................................................................... 64
8 Memory Map to PCI Express Device Configuration Space ............................................... 79
9 MCH Configuration Cycle Flow Chart ........................................................................... 80
10 GMCH Graphics Controller Block Diagram .................................................................. 532
11 HDMI Overview...................................................................................................... 537
12 Display Port Overview............................................................................................. 538
13 Display configurations on ATX Platforms.................................................................... 540
14 Display Configurations on Balanced Technology Extended (BTX) Platforms ..................... 541
15 Example of EIT Usage Model.................................................................................... 543
16 DMA Address Translation ........................................................................................ 545
17 Platform Clocking Diagram ...................................................................................... 554
18 GMCH Ballout Diagram (Top View Left – Columns 45–31) ............................................ 570
19 GMCH Ballout Diagram (Top View Left – Columns 30–16) ............................................ 571
20 GMCH Ballout Diagram (Top View Left – Columns 15–1).............................................. 572
21 (G)MCH Package Drawing ....................................................................................... 597
22 JTAG Boundary Scan Test Mode Initialization Cycles ................................................... 599
23 JTAG Test Mode Initialization Cycles ......................................................................... 601
24 XOR Test Mode Initialization Cycles .......................................................................... 602
Tables
1 Intel^® Series 4 Chipset High-Level Feature Component Differences................................. 22
2 Intel Specification .................................................................................................... 29
3 SDVO, Display Port, HDMI/DVI, PCI Express* Signal Mapping ........................................ 47
4 Expansion Area Memory Segments ............................................................................. 59
5 Extended System BIOS Area Memory Segments........................................................... 59
6 System BIOS Area Memory Segments......................................................................... 60
7 Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT Stolen and 1 MB TSEG
62
8 Transaction Address Ranges – Compatible, High, and TSEG ........................................... 70
9 SMM Space Table ..................................................................................................... 70
10 SMM Control Table ................................................................................................... 71
11 DRAM Controller Register Address Map (D0:F0) ........................................................... 85
12 DRAM Rank Attribute Register Programming .............................................................. 130
13 PCI Express* Register Address Map (D1:F0) .............................................................. 173
14 Host-Secondary PCI Express* Bridge Register Address Map (D6:F0) ............................. 229
15 Integrated Graphics Register Address Map (D2:F0)..................................................... 275
16 PCI Register Address Map (D2:F1)............................................................................ 297
17 HECI Function in ME Subsystem Register Address Map ................................................ 315
18 Second HECI Function in ME Subsystem Register Address Map ..................................... 328
19 HECI PCI MMIO space Register Address Map .............................................................. 340
20 Second HECI function MMIO Space Register Address Map ............................................ 344
21 IDE Function for remote boot and Installations PT IDER Register Address Map................ 348
22 IDE BAR0 Register Address Map............................................................................... 361
23 IDE BAR4 Register Address Map............................................................................... 377
24 Serial Port for Remote Keyboard and Text (KT) Redirection Register Address Map........... 386
25 KT IO/ Memory Mapped Device Register Address Map ................................................. 399
26 Intel^® Virtualization Technology For Directed I/O Register Address Map ........................ 425
Datasheet
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