AC82G41SLGQ3 Datasheet, PDF (239/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.14
SSTS1—Secondary Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
1E–1Fh
0000h
RO, RWC
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side of the "virtual" PCI-PCI bridge embedded within MCH.
Bit
15
14
13
12
11
10:9
8
7
6
5
4:0
Access
RWC
RWC
RWC
RWC
RO
RO
RWC
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
00b
0b
0b
0b
0b
00h
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Description
Detected Parity Error (DPE): This bit is set by the Secondary Side
for a Type 1 Configuration Space header device whenever it receives a
Poisoned Transaction Layer Packet, regardless of the state of the
Parity Error Response Enable bit in the Bridge Control Register.
Received System Error (RSE): This bit is set when the Secondary
Side for a Type 1 configuration space header device receives an
ERR_FATAL or ERR_NONFATAL.
Received Master Abort (RMA): This bit is set when the Secondary
Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Unsupported Request Completion Status.
Received Target Abort (RTA): This bit is set when the Secondary
Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Completer Abort Completion Status.
Signaled Target Abort (STA): Not Applicable or Implemented.
Hardwired to 0. The MCH does not generate Target Aborts (the MCH
will never complete a request using the Completer Abort Completion
status).
DEVSELB Timing (DEVT): Not Applicable or Implemented.
Hardwired to 0.
Master Data Parity Error (SMDPE): When set, indicates that the
MCH received across the link (upstream) a Read Data Completion
Poisoned Transaction Layer Packet (EP=1). This bit can only be set
when the Parity Error Enable bit in the Bridge Control register is set.
Fast Back-to-Back (FB2B): Not Applicable or Implemented.
Hardwired to 0.
Reserved
66/60 MHz capability (CAP66): Not Applicable or Implemented.
Hardwired to 0.
Reserved
Datasheet
239