AC82G41SLGQ3 Datasheet, PDF (487/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
49
48
47:32
31:0
Access
R/W
R/W
R/W
RO
Default
Value
000000h
00h
0000h
00000000h
RST/PWR
Description
Core
Core
Core
Core
Drain Reads (DR): This field is ignored by hardware if the
DRD field is reported as clear in the Capability register.
When DRD field is reported as set in the Capability register,
the following encodings are supported for this field:
0 = Hardware may complete the IOTLB invalidation
without draining any translated DMA reads that are
queued in the root-complex and yet to be processed.
1 = Hardware must drain all/relevant translated DMA
reads that are queued in the root-complex before
indicating IOTLB invalidation completion to software.
A DMA read request to system memory is defined as
drained when root-complex has finished fetching all of its
read response data from memory.
Drain Writes (DW): This field is ignored by hardware if
the DWD field is reported as clear in the Capability register.
When DWD field is reported as set in the Capability
register, the following encodings are supported for this
field:
0 = Hardware may complete the IOTLB invalidation
without draining any translated DMA writes that are
queued in the root-complex for processing.
1 = Hardware must drain all/relevant translated DMA
writes that are queued in the root-complex before
indicating IOTLB invalidation completion to software.
A DMA write request to system memory is defined as
drained when the effects of the write is visible to processor
accesses to all addresses targeted by the DMA write.
Domain-ID (DID): This field indicates the id of the
domain whose IOTLB entries needs to be selectively
invalidated. This field must be programmed by software for
domain-selective, domainpage-selective and device-page-
selective invalidation requests.
The Capability register reports the domain-ID width
supported by hardware. Software must ensure that the
value written to this field is within this limit.
Hardware may ignore and not implement bits 47:(32+N)
where N is the supported domain-ID width reported in the
capability register.
Reserved
Datasheet
487