AC82G41SLGQ3 Datasheet, PDF (202/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.38
LCAP—Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
AC-AFh
02214D02h
RO, R/WO
32 bits
This register indicates PCI Express device specific capabilities.
Bit
Access
31:24
RO
23:22
RO
21
RO
20
RO
19
RO
Default
Value
02h
00b
1b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Port Number (PN): This field indicates the PCI Express
port number for the given PCI Express link. This field
matches the value in Element Self Description[31:24].
Reserved
Link Bandwidth Notification Capability (LBNC): A
value of 1b indicates support for the Link Bandwidth
Notification status and interrupt mechanisms. This
capability is required for all Root Ports and Switch
downstream ports supporting Links wider than x1 and/or
multiple Link speeds.
This field is not applicable and is reserved for Endpoint
devices, PCI Express to PCI/PCI-X bridges, and Upstream
Ports of Switches.
Devices that do not implement the Link Bandwidth
Notification capability must hardwire this bit to 0b.
Data Link Layer Link Active Reporting Capable
(DLLLARC): For a Downstream Port, this bit must be set
to 1b if the component supports the optional capability of
reporting the DL_Active state of the Data Link Control and
Management State Machine. For a hot-plug capable
Downstream Port (as indicated by the Hot-Plug Capable
field of the Slot Capabilities register), this bit must be set
to 1b.
For Upstream Ports and components that do not support
this optional capability, this bit must be hardwired to 0b.
Surprise Down Error Reporting Capable (SDERC): For
a Downstream Port, this bit must be set to 1b if the
component supports the optional capability of detecting
and reporting a Surprise Down error condition.
For Upstream Ports and components that do not support
this optional capability, this bit must be hardwired to 0b.
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Datasheet