AC82G41SLGQ3 Datasheet, PDF (384/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.8.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor
Table Pointer Register Byte 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
Ch
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition of the function.
This register implements the Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the secondary channel. This register is
read/write by the HOST interface.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 0 (DTPB0):
10.8.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor
Table Pointer Register Byte 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
Dh
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition of the function.
This register implements the Byte 1 (of four bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the secondary channel. This register is
programmed by the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 1 (DTPB1):
10.8.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor
Table Pointer Register Byte 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
Eh
00h
R/W
8 bits
Reset: Host system Reset or D3->D0 transition of the function.
This register implements the Byte 2 (of four bytes) of the descriptor table Pointer (four
I/O byte addresses) for bus master operation of the secondary channel. This register is
programmed by the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Descriptor Table Pointer Byte 2 (DTPB2):
384
Datasheet