AC82G41SLGQ3 Datasheet, PDF (351/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.4
RID—Revision ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
8h
02hsee description below
RO
8 bits
This register specifies a device specific revision.
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
see
description
Core
Revision ID. Refer to the Intel^® 4 Series Chipset Family
Specification Update for the value of this register.
10.5.5
CC—Class Codes
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
9-Bh
010185h
RO
24 bits
This register identifies the basic functionality of the device ie IDE mass storage.
Bit
23:0
Access
RO
Default
Value
010185h
RST/PWR
Description
Core
Programming Interface BCC SCC (PI BCC SCC):
10.5.6
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
Ch
00h
RO
8 bits
This register defines the system cache line size in DWORD increments. Mandatory for
master which use the Memory-Write and Invalidate command.
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Cache Line Size (CLS): All writes to system memory are
Memory Writes.
Datasheet
351