AC82G41SLGQ3 Datasheet, PDF (364/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.5
IDESCIR—IDE Sector Count In Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
2h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Sector Count register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDESCIR, IDESCOR0, IDESCOR1) are updated with the written
value.
A host read to this register address reads the IDE Sector Count Out Register IDESCOR0
if DEV=0 or IDESCOR1 if DEV=1
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Sector Count Data (IDESCD): Host writes the
number of sectors to be read or written.
10.6.6
IDESCOR1—IDE Sector Count Out Register Dev1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
2h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the HOST interface if DEV = 1. ME-Firmware writes to this
register at the end of a command of the selected device.
When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this
register is updated.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Sector Count Out Dev1 (ISCOD1): Sector Count
register for Slave Device ie Device 1
364
Datasheet