AC82G41SLGQ3 Datasheet, PDF (109/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.25
LAC—Legacy Access Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
97h
00h
R/W, R/W/L, RO
8 bits
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
Bit
Access
7
R/W/L
6:2
1
(82P45 MCH
only)
1
(82Q45,
82Q43, 82B43,
82G45, 82G43,
82G41 GMCH
and 82P43
MCH only)
RO
R/W
R/W
Default
Value
0b
00h
0b
0b
RST/
PWR
Core
Core
Core
Description
Hole Enable (HEN): This field enables a memory hole in
DRAM space. The DRAM that lies "behind" this space is
not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
This bit is Intel TXT lockable (82Q45/82Q43 GMCH only).
Reserved
PEG1 MDA Present (MDAP1): Definition of this bit is
the same as for the adjacent PEG0 MDA Present bit
except for all references to Device 1 are replaced with
Device 6.
Core Reserved
Datasheet
109