AC82G41SLGQ3 Datasheet, PDF (31/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Introduction
1.2.2
1.2.3
System Memory Interface
The (G)MCH integrates a system memory DDR2/DDR3 controller with two, 64-bit wide
interfaces. The buffers support both SSTL_1.8 (Stub Series Terminated Logic for 1.8 V)
and SSTL_1.5 (Stub Series Terminated Logic for 1.5V) signal interfaces. The memory
controller interface is fully configurable through a set of control registers.
System Memory Interface Details
• Directly supports one or two channels of DDR2 or DDR3 memory with a maximum
of two DIMMs per channel.
• Supports single and dual channel memory organization modes.
• Supports a data burst length of eight for all memory organization modes.
• Supported memory data transfer rates:
— 667 MHz and 800 MHz for DDR2
— 800 MHz and 1066 MHz for DDR3.
• I/O Voltage of 1.8 V for DDR2 and 1.5 V for DDR3.
• Supports both un-buffered non-ECC DDR2 or non-ECC DDR3 DIMMs.
• Supports maximum memory bandwidth of 6.4 GB/s in single-channel mode or
12.8 GB/s in dual-channel mode assuming DDR2 800 MHz.
• Supports 512-Mb, 1-Gb, 2-Gb DDR2 and 512-Mb, 1-Gb DDR3 DRAM technologies
for x8 and x16 devices.
• Using 512 Mb device technologies, the smallest memory capacity possible is
256 MB, assuming Single Channel Mode with a single x16 single sided un-buffered
non-ECC DIMM memory configuration.
• Using 2 Gb device technologies, the largest memory capacity possible is 16 GB,
assuming Dual Channel Mode with four x8 double sided un-buffered non-ECC or
ECC DIMM memory configurations.
NOTE: The ability to support greater than the largest memory capacity is subject to
availability of higher density memory devices.
• Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of 8
bank devices)
• Supports opportunistic refresh scheme
• Supports Partial Writes to memory using Data Mask (DM) signals
• Supports a memory thermal management scheme to selectively manage reads
and/or writes. Memory thermal management can be triggered either by on-die
thermal sensor, or by preset limits. Management limits are determined by weighted
sum of various commands that are scheduled on the memory interface.
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and
ICH10/ICH7. This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH10/ICH7 supports two virtual channels on DMI: VC0 and VC1.
These two channels provide a fixed arbitration scheme where VC1 is always the highest
Datasheet
31