AC82G41SLGQ3 Datasheet, PDF (375/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.7 IDE BAR1
10.7.1
Address
Offset
2h
2h
Register
Symbol
IDDCR
IDASR
Register Name
IDE Device Control Register
IDE Alternate status Register
Default
Value
00h
00h
Access
RO, WO
RO/V
IDDCR—IDE Device Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR1
2h
00h
RO, WO
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Device Control register of the Control block of the IDE
function. This register is Write only by the Host.
When the HOST reads to the same address it reads the Alternate Status register.
Bit
Access
Default
Value
RST/PWR
Description
7:3
RO
00000b
Core
Reserved: Writable by Host, but no hardware affect due to
writes.
2
WO
0b
Core
Software reset (S_RST): When this bit is set by the
Host, it forces a reset to the device.
1
WO
0
RO
0b
Core
Host interrupt Disable (nIEN): When set, this bit
disables hardware from sending interrupt to the Host.
0b
Core
Reserved: Writable by Host, but no hardware affect due to
writes
Datasheet
375