AC82G41SLGQ3 Datasheet, PDF (407/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.11 KTMSR—KT Modem Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
6h
00h
RO, RO/CR
8 bits
Reset: Host system Reset or D3->D0 transition
The functionality of the Modem is emulated by the FW. This register provides the status
of the current state of the control lines from the modem.
Bit
Access
Default
Value
RST/PWR
Description
7
RO
0b
6
RO
0b
5
RO
0b
4
RO
0b
3
RO/CR
0b
2
RO/CR
0b
1
RO/CR
0b
0
RO/CR
0b
Core
Core
Core
Core
Core
Core
Core
Core
Data Carrier Detect (DCD): In Loop Back mode this bit is
connected by hardware to the value of MCR bit 3.
Ring Indicator (RI): In Loop Back mode this bit is
connected by hardware to the value of MCR bit 2.
Data Set Ready (DSR): In Loop Back mode this bit is
connected by hardware to the value of MCR bit 0.
Clear To Send (CTS): In Loop Back mode this bit is
connected by hardware to the value of MCR bit 1.
Delta Data Carrier Detect (DDCD): This bit is set when
bit 7 is changed. This bit is cleared by hardware when the
MSR register is being read by the HOST driver.
Trailing Edge of Read Detector (TERI): This bit is set
when bit 6 is changed from 1 to 0. This bit is cleared by
hardware when the MSR register is being read by the Host
driver.
Delta Data Set Ready (DDSR): This bit is set when bit 5
is changed. This bit is cleared by hardware when the MSR
register is being read by the Host driver.
Delta Clear To Send (DCTS): This bit is set when bit 4 is
changed. This bit is cleared by hardware when the MSR
register is being read by the Host driver.
10.10.12 KTSCR—KT Scratch Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
7h
00h
R/W
8 bits
Reset: Host system reset or D3->D0 transition
This register has no affect on hardware. This is for the programmer to hold data
temporarily.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Scratch Register Data (SCRD):
Datasheet
407