AC82G41SLGQ3 Datasheet, PDF (562/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Electrical Characteristics
14.3.2 General DC Characteristics
Platform Reference Voltages at the top of Table 51 are specified at DC only. V_REF
measurements should be made with respect to the supply voltage.
Table 51. DC Characteristics
Symbol
Parameter
Min
Nom
Max
Unit Notes
Reference Voltages
FSB_DVREF
FSB_ACCVREF
Host Data, Address, and
Common Clock Signal
Reference Voltages
FSB_SWING
Host Compensation Reference
Voltage
CL_VREF
Controller Link Reference
Voltage
DDR_VREF DDR2 Reference Voltage
DDR_VREF DDR3 Reference Voltage
0.635 x
VTT_FSB – 2%
0.25 x VTT_FSB
– 2%
0.3325
0.85
0.70
0.635 x
VTT_FSB
0.25 x
VTT_FSB
0.35
0.9
0.75
0.635 x
VTT_FSB + 2%
V
0.25 x VTT_FSB
+ 2%
V
0.3675
V
0.95
V
0.80
V
Host Interface
V_{IL_H}
V_{IH_H}
V_{OL_H}
V_{OH_H}
I_{OL_H}
Host GTL+ Input Low Voltage
-0.072
Host GTL+ Input High Voltage
Host GTL+ Output Low
Voltage
Host GTL+ Output High
Voltage
Host GTL+ Output Low
Current
(0.635 x
VTT_FSB) +
0.072
—
VTT_FSB –
0.072
—
I_{LEAK_H}
C_PAD
C_PCKG
Host GTL+ Input Leakage
Current
Host GTL+ Input Capacitance
Host GTL+ Input Capacitance
(common clock)
—
1.5
TBD
0
VTT_FSB
—
—
—
—
—
—
(0.635 x
VTT_FSB) –
V
0.072
VTT_FSB +
0.072
V
(0.25 x
VTT_FSB) +
V
0.072
VTT_FSB
V
VTT_FSBmax *
(1 – 0.25) /
Rtt_min
TBD
2.5
Rtt_min
mA
=
47.5 Ω
V_OL<
μA
Vpad<
VTT_F
SB
pF
TBD
pF
DDR2 System Memory Interface
V_IL(DC)
V_IH(DC)
V_IL(AC)
V_IH(AC)
V_OL
DDR2 Input Low Voltage
DDR2 Input High Voltage
DDR2 Input Low Voltage
DDR2 Input High Voltage
DDR2 Output Low Voltage
DDR_VREF –
100 mV
DDR_VREF –
100 mV
DDR_VREF –
100 mV
V
DDR_VREF + DDR_VREF + DDR_VREF +
100 mV
100 mV
100 mV
V
DDR_VREF –
125 mV
DDR_VREF –
125 mV
DDR_VREF –
125 mV
V
DDR_VREF + DDR_VREF + DDR_VREF +
125 mV
125 mV
125 mV
V
0.6
0.64
0.67
V
1
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