AC82G41SLGQ3 Datasheet, PDF (161/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.43
TSS—Thermal Sensor Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CDAh
00h
RO
8 bits
This read only register provides trip point and other status of the thermal sensor.
All bits in this register are reset to their defaults by MPWROK.
Bit
Access
Default
Value
RST/PWR
Description
7
RO
6
RO
5
RO
4
RO
3:2
RO
1
RO
0
RO
Catastrophic Trip Indicator (CTI):
0b
Core
1 = Internal thermal sensor temperature is above the
catastrophic setting.
Hot Trip Indicator (HTI):
0b
Core
1 = Internal thermal sensor temperature is above the Hot
setting.
Aux0 Trip Indicator (A0TI):
0b
Core
1 = A 1 indicates that the internal thermal sensor
temperature is above the Aux0 setting.
Thermometer Mode Output Valid (TOV):
1 = Thermometer mode is able to converge to a
temperature and that the TR register is reporting a
0b
Core
reasonable estimate of the thermal sensor
temperature.
0 = Thermometer mode is off, or that temperature is out of
range, or that the TR register is being looked at before
a temperature conversion has had time to complete.
00b
Core
Reserved
Direct Catastrophic Comparator Read (DCCR): This bit
0b
Core
reads the output of the Catastrophic comparator directly,
without latching via the Thermometer mode circuit. Used
for testing.
Direct Hot Comparator Read (DHCR): This bit reads the
0b
Core
output of the Hot comparator directly, without latching via
the Thermometer mode circuit. Used for testing.
Datasheet
161