AC82G41SLGQ3 Datasheet, PDF (422/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Trusted Execution Technology Registers (Intel^® 82Q45 and 82Q43 GMCH Only)
11.1.25 TXT.CMD.SECRETS—TXT Secrets Command
The ILP SINIT code does this to tell the chipset that there are going to be secrets in
memory. This is used when determining whether to block memory after a reset or
power failure.
11.1.26 TXT.CMD.NO-SECRETS—TXT Secrets Command
The CPU that authenticates the SEXIT code does this to tell the chipset that there are
no more secrets in memory. It is also used by the Authenticated Code that wipes
secrets from memory after a reset.
11.1.27 TXT.E2STS—TXT Extended Error Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/TXT Specific
8F0-8F7h
0000000000000000h
RO
64 bits
This register is used to read the status associated with various errors that might be
detected. The bits in this register are only valid if the TXT.WAKE-ERROR.STS bit is set in
the TXT.ESTS register. The bits in this register are all sticky. The default value is
undefined.
Bit Access
63:33
RO
32
RO
31:3
RO
2
RO
1
RO
0
RO
Default
Value
0h
0b
0b
0b
0b
0b
Description
Reserved
TXT Reset Policy (TXT.RESET.POLICY): When cleared to '0', an assertion of
the TXTRESET# pin will cause a full system reset, whereby the ICH does a
handshake with the MCH before asserting the Platform Reset. When set to '1',
the ICH will do a power cycle of the platform on an assertion of TXTRESET#.
Default=0.
Reserved
TXT Memory Block Status (TXT.BLOCK-MEM.STS): This bit indicates if the
ICH has indicated to the MCH that it should block memory accesses. Reset only
by RTEST#.
TXT Secrets Status (TXT.SECRETS.STS): This bit indicates if there are any
potential secrets in memory. This is used in the setting of the various flags.
Reset only by RTEST#.
TXT Sleep entry error status (TXT.SLP-ENTRY-ERROR.STS): This bit
indicates if there has been an improper attempt to go to sleeping state.
Reset only by RTEST#.
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Datasheet