AC82G41SLGQ3 Datasheet, PDF (258/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
8
RO
0b
7
RW
0b
6
RW
0b
5
RW/SC
0b
4
RW
0b
3
RO
0b
2
RW
0b
1:0
RW
00b
Core
Core
Core
Core
Core
Core
Core
Core
Enable Clock Power Management (ECPM): Applicable only for
form factors that support a "Clock Request" (CLKREQ#)
mechanism, this enable functions as follows:
0 = Clock power management is disabled and device must hold
CLKREQ# signal low
1 = The device is permitted to use CLKREQ# signal to power
manage link clock according to protocol defined in appropriate
form factor specification.
Default value of this field is 0b.
Components that do not support Clock Power Management (as
indicated by a 0b value in the Clock Power Management bit of the
Link Capabilities Register) must hardwire this bit to 0b.
Reserved
Common Clock Configuration (CCC):
0 = Indicates that this component and the component at the
opposite end of this Link are operating with asynchronous
reference clock.
1 = Indicates that this component and the component at the
opposite end of this Link are operating with a distributed
common reference clock.
The state of this bit affects the N_FTS value advertised during link
training.
Retrain Link (RL):
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical Layer
LTSSM from L0 or L1 states to the Recovery state.
This bit always returns 0 when read.
This bit is cleared automatically (no need to write a 0).
It is permitted to write 1b to this bit while simultaneously writing
modified values to other fields in this register. If the LTSSM is not
already in Recovery or Configuration, the resulting Link training
must use the modified values. If the LTSSM is already in Recovery
or Configuration, the modified values are not required to affect the
Link training that's already in progress.
Link Disable (LD):
0 = Normal operation.
1 = Link is disabled. Forces the LTSSM to transition to the Disabled
state (via Recovery) from L0 or L1 states. Link retraining
happens automatically on 0 to 1 transition, just like when
coming out of reset.
Writes to this bit are immediately reflected in the value read from
the bit, regardless of actual Link state.
Read Completion Boundary (RCB): Hardwired to 0 to indicate
64 byte.
Reserved
Active State PM (ASPM): Controls the level of active state power
management supported on the given link.
00 = Disabled
01 = Reserved
10 = Reserved
11 = L1 Entry Supported
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Datasheet