AC82G41SLGQ3 Datasheet, PDF (520/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
59:57
RO
56:50
RO
49
R/W
Default
Value
1h
0
0
RST/PWR
Description
Core
Core
Core
IOTLB Actual Invalidation Granularity (IAIG):
Hardware reports the granularity at which an invalidation
request was proceed through this field at the time of
reporting invalidation completion (by clearing the IVT
field).
000 = Reserved. This indicates hardware detected an
incorrect invalidation request and hence ignored the
request. Examples of incorrect invalidation requests
include specifying a reserved value in the IIRG field
or specifying an unsupported address mask value in
IVA_REG for page-selective invalidation requests.
001 = Global Invalidation performed. This could be in
response to a global, domain-selective, domain-
page-selective, or device-page-selectiveinvalidation
request.
010 = Domain-selective invalidation performed using the
domain-ID specified by software in the DID field.
This could be in response to a domain-selective,
domain-page-selective, or device-page-selective
invalidation request.
011 = Domain-page-selective invalidation performed using
the address, mask and hint specified by software in
the Invalidate Address register and domain-ID
specified in DID field. This can be in response to a
domain-page-selective or device-page-selective
invalidation request.
100 = Device-page-selective invalidation performed using
the address, mask and hint specified by software in
the Invalidate Address register and device-ID
specified in SID field. This can only be in response
to a device-page-selective invalidation request.
101 - 111 =Reserved.
Reserved
Drain Reads (DR): This field is treated as reserved if the
DRD field is reported as clear in the Capability register.
0 = Hardware may complete the IOTLB invalidation
without draining any translated DMA reads that are
queued in the root-complex and yet to be processed.
1 = Hardware must drain all/relevant translated DMA reads
that are queued in the root-complex before indicating
IOTLB invalidation completion to software. A DMA read
request to system memory is defined as drained when
root-complex has finished fetching all of its read
response data from memory.
520
Datasheet