AC82G41SLGQ3 Datasheet, PDF (235/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
INTA Status (INTAS): Indicates that an interrupt message is
3
RO
0b
Core
pending internally to the device. Only PME sources feed into this
status bit (not PCI INTA-INTD assert and de-assert messages). The
INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit.
2:0
RO
000b
Core Reserved
8.5
RID1—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
8h
see description below
RO
8 bits
This register contains the revision number of the MCH device 6. These bits are read
only and writes to this register have no effect.
Bit
7:0
8.6
Access
RO
Default
Value
see
description
RST/
PWR
Core
Description
Revision Identification Number (RID1): This is an 8-bit value
that indicates the revision identification number for the MCH Device
0. Refer to the Intel^® 4 Series Chipset Specification Update for the
value of this register.
CC1—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
9–Bh
060400h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
Bit
23:16
15:8
7:0
Access
RO
RO
RO
Default
Value
06h
04h
00h
RST/
PWR
Core
Core
Core
Description
Base Class Code (BCC): Indicates the base class code for this
device. This code has the value 06h, indicating a Bridge device.
Sub-Class Code (SUBCC): Indicates the sub-class code for this
device. The code is 04h indicating a PCI to PCI Bridge.
Programming Interface (PI): Indicates the programming interface
of this device. This value does not specify a particular register set
layout and provides no practical use for this device.
Datasheet
235