AC82G41SLGQ3 Datasheet, PDF (382/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.8.9
IDESBMCR—IDE Secondary Bus Master Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
8h
00h
RO, R/W
8 bits
Reset: See specific bits
This register implements the bus master command register of the secondary channel.
This register is programmed by the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:4
RO
0h
Core
Reserved
Read Write Command (RWC): This bit sets the direction
of bus master transfer. When 0, Reads are performed from
system memory; when 1, writes are performed to System
3
R/W
0b
Core
Memory. This bit should not be changed when the bus
master function is active.
Reset: Host system Reset or D3->D0 transition of function
2:1
RO
00b
Core
Reserved
Start/Stop Bus Master (SSBM): This bit gates the bus
master operation of IDE function when zero.
Writing 1 enables the bus master operation. Bus master
operation can be halted by writing a 0 to this bit.
0
R/W
0b
Core
Operation cannot be stopped and resumed.
This bit is cleared after data transfer is complete as
indicated by either the BMIA bit or the INT bit of the Bus
Master status register is set or both are set.
Reset: Host system Reset or D3->D0 transition of function
10.8.10 IDESBMDS0R—IDE Secondary Bus Master Device Specific
0 Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
9h
00h
R/W
8 bits
Reset: ME System Reset
This register implements the bus master Device Specific 1 register of the secondary
channel. This register is programmed by the Host.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W
00h
Core
Device Specific Data0 (DSD0): Device Specific
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