AC82G41SLGQ3 Datasheet, PDF (303/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.2.10
MMADR—Memory Mapped Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
10-17h
0000000000000004h
R/W, RO
64 bits
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB and the base address is defined by bits [31:19].
Bit
63:36
35:20
19:4
3
2:1
0
Access
R/W
R/W
RO
RO
RO
RO
Default
Value
0000000h
0000h
0000h
0b
10b
0b
RST/PWR
Description
FLR, Core
FLR, Core
Core
Core
Core
Core
Reserved
Memory Base Address (MBA): Set by the OS, these bits
correspond to address signals 35:20.
Address Mask (ADMSK): Hardwired to 0s to indicate
512 KB address range (aligned to 1 MB boundary).
Prefetchable Memory (PREFMEM): Hardwired to 0 to
prevent prefetching.
Memory Type (MEMTYP): Hardwired to 10b to indicate
64-bit address.
Memory / IO Space (MIOS): Hardwired to 0 to indicate
memory space.
9.2.11
SVID2—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
2C-2Dh
0000h
RO
16 bits
Bit
15:0
Access
RO
Default
Value
0000h
RST/PWR
Description
Core
Subsystem Vendor ID (SUBVID): This value is used to
identify the vendor of the subsystem. This register should
be programmed by BIOS during boot-up. Once written, this
register becomes Read Only.
This register can only be cleared by a Reset.
Datasheet
303