AC82G41SLGQ3 Datasheet, PDF (214/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.50
LCTL2—Link Control 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
D0-D1h
0002h
R/W/P, R/W, RO
16 bits
Bit
15:13
Access
RO
12
R/W/P
11
R/W/P
10
R/W/P
Default
Value
000b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Compliance De-emphasis: This bit sets the de-emphasis
level in Polling.Compliance state if the entry occurred due
to the Enter Compliance bit being 1b.
1 = 3.5 dB
0 = 6 dB
When the Link is operating at 2.5 GT/s, the setting of this
bit has no effect. Components that support only 2.5 GT/s
speed are permitted to hardwire this bit to 0b.
For a Multi-Function device associated with an Upstream
Port, the bit in Function 0 is of type R/WS, and only
Function 0 controls the component's Link behavior. In all
other Functions of that device, this bit is of type RSVD.
This bit is intended for debug, compliance testing
purposes.
System firmware and software is allowed to modify this bit
only during debug or compliance testing.
Compliance SOS (compsos): When set to 1b, the
LTSSM is required to send SKP Ordered Sets periodically in
between the (modified) compliance patterns.
For a Multi-Function device associated with an Upstream
Port, the bit in Function 0 is of type R/WS, and only
Function 0 controls the component's Link behavior. In all
other Functions of that device, this bit is of type RSVD.
Components that support only the 2.5 GT/s speed are
permitted to hardwire this field to 0b.
Enter Modified Compliance (entermodcompliance):
When this bit is set to 1b, the device transmits modified
compliance pattern if the LTSSM enters Polling.Compliance
state.
Components that support only the 2.5GT/s speed are
permitted to hardwire this bit to 0b.
214
Datasheet